一种基于自偏置技术的低抖动锁相环  

A Low Jitter PLL Based on Self-Biased Technique

作　　者：盛炜[1,2] 张国华[1,2] 杨霄垒 张沁枫 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2017年第3期351-354,共4页Microelectronics

基　　金：333高层次人才培养工程专项资助项目(2007124)

摘　　要：设计了一种环路带宽与输入频率的比值固定的自偏置锁相环。对VCO延迟单元进行改进,降低了抖动。采用SMIC 65nm CMOS工艺,在1.2V的工作电压下对锁相环进行仿真,输出频率范围为0.5~3.125 GHz。仿真结果表明,在输出频率1.875 GHz处的峰峰值抖动为8.7ps,电路的核心功耗为45mW,相位噪声为-79.7dBc/Hz。A self-biased PLL with fixed ratio of loop bandwidth to input frequency was designed. The VCO＇s delay elements were optimized to reduce the jitter. The proposed PLL was simulated in the SMIC 65 nm CMOS process at 1.2 V power supply. Its output frequency was 0.5 GHz to 3. 125 GHz. Simulation results showed that the PLL had a peak-to-peak jitter of 8.7 ps at 1. 875 GHz output frequency with a power of 32 mW and a phase noise of -79.7 dBc/Hz.

关 键 词：自偏置 锁相环 压控振荡器 低抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学]