基于改进的电流传送器的模拟乘法器设计  

Four-Quadrant Multiplier Based on Modified Differential Difference Current Conveyor

作　　者：王春悦[1] 梁潇[1] 石文孝[1] 

机构地区：[1]吉林大学通信工程学院,长春130012

出　　处：《吉林大学学报（信息科学版）》2017年第3期229-234,共6页Journal of Jilin University（Information Science Edition）

基　　金：国家自然科学基金资助项目(61373124)

摘　　要：为优化四象限模拟乘法器的电路性能,以满足现代模拟信号处理电路高频低噪的应用要求,提出了一种新型低压四象限模拟乘法器。该乘法器以基于改进的电流传送器(MDDCC:Modified Differential Difference Current Conveyor)的模拟平方器为基本电路,采用台湾积体电路制造公司的0.18μm CMOS工艺的PSPICE(Personal Simulation Program with Integrated Circuit Emphasis)计算机软件进行仿真。仿真结果表明,该四象限乘法器具有良好线性,输入电压的范围为-0.1 V^+0.1 V,截止频率为451.307 MHz,当输入电压峰值为100 mV时,输出噪声电压小于150 nV。与已有乘法器比较,该乘法器电路具有较好的线性特性以及较高的截止频率和带宽,输出噪声电压有所减少,在高频信号处理系统中性能更优。In order to optimize the performance of four-quadrant analog multiplier,to meet the application requirements of modern analog signal processing circuit such as high-frequency and low-noise,a new low voltage four-quadrant analog multiplier is proposed. The multiplier circuit uses the analog squarer based on MDDCC（ Modified Differential Difference Current Conveyor） as a basic module. The function of multiplying circuit is confirmed by PSPICE（ Personal Simulation Program with Integrated Circuit Emphasis） simulations using TSMC 0. 18 μm CMOS technology. The proposed circuit has a good linearity. The range of input voltage is-0. 1 V ~ ＋ 0. 1 V,the-3 d B bandwidth of the proposed circuit is 451. 307 MHz and the output noise voltage is less than 150 nV when the peak value of input voltage is 100 mV. By comparing with some available multipliers in references,the proposed multiplier circuit has better linearity,higher cut-off frequency and reduces the output noise voltage. The four-quadrant analog multiplier has good performance in the high frequency signal processing system.

关 键 词：集成电路 模拟乘法器 改进的电流传送器 PSPICE仿真 

分 类 号：TN713.8[电子电信—电路与系统]