基于FPGA的AES算法硬件实现优化及IP核应用  

Optimization of AES algorithm hardware implementation based on FPGA and application of its IP core

作　　者：龚向东[1] 王佳[2] 张准[2] 王坤[2] GONG Xiang-dong WANG Jia ZHANG Zhun WANG Kun(College of Electronic Science and Technology , Shenzhen University,Shenzhen 518060,China College of Optoelectronic Engineering, Shenzhen University ,Shenzhen 518060,China)

机构地区：[1]深圳大学电子科学与技术学院,广东深圳518060 [2]深圳大学光电工程学院,广东深圳518060

出　　处：《电子设计工程》2017年第12期1-5,共5页Electronic Design Engineering

基　　金：国家自然科学基金仪器专项(61027014)

摘　　要：根据AES算法的特点,从3方面对算法硬件实现进行改进:列混合部分使用查找表代替矩阵变换,降低算法实现的运算复杂度,采用流水线结构优化关键路径-密钥拓展,提升加密速度,利用FPGA定制RAM(BRAM)预存查找表进一步提升加密速度。优化后的AES算法在Virtex-6xc6vlx240T(速度等级-3)FPGA上实现,结果发现,AES算法共占用1 139个Slice,最大频率达到443.99 MHz,通量达到56.83 Gbit/s,效率达到49.89(Mbit/s)/Slice;然后,对AES算法进行接口逻辑声明,将优化后AES算法封装成自定制IP核;最后,采用基于NIOS II的SOPC技术,构建了一个嵌入式AES算法加密系统,实现了数据通信中的高速加密。According to the characteristics of AES algorithm , its hardware implementation is improved from three aspects in this paper： In parts of sub_Bytes and MixColumns , using lookup table replace matrix transform to reduce the computational complexity of AES algorithm implementation; Using pipeline architecture for optimization of critical path greatly increase encryption speed;Employing FPGA customized RAM （BRAM） store pre- computed lookup table value to further enhance the encryption speed. The optimized AES algorithm is simulated and verified , then it is implemented on a Xilinx Virtex-6 xc6vlx240T （speed grade -3） FPGA. Improved results are obtained： 1139 Slices is totally employed, maximum frequency is 443.99 MHz, throughput is 56.83 Gbit/s, and efficiency is 49.89 （Mbit/s）/Slice; Then, declaring Interface logic for AES algorithm, the optimized AES algorithm is encapsulated into a custom IP core; At last , using SOPC technology to build an embedded AES algorithm encryption system based on NIOS Ⅱ , the system implement high speed data encryption in data communication.

关 键 词：流水线结构 通量 效率 自定制IP核 加密系统 

分 类 号：TN918[电子电信—通信与信息系统]