面向分组密码的可重构异构多核并行处理架构  

Reconfigurable Asymmetrical Multi-core Architecture for Block Cipher

作　　者：冯晓[1] 李伟[2] 戴紫彬[1] 马超[1] 李功丽[1] 

机构地区：[1]解放军信息工程大学,河南郑州450000 [2]复旦大学专用集成电路与系统国家重点实验室,上海20123

出　　处：《电子学报》2017年第6期1311-1320,共10页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61404175)

摘　　要：现有的可重构分组密码实现结构中,专用指令处理器吞吐率不高,阵列结构资源利用率低、算法映射过程复杂.为此,设计了分组密码可重构异构多核并行处理架构RAMCA(Reconfigurable Asymmetrical Multi-Core Architecture),分析了典型SP(AES-128)、Feistel(SMS4)、L-M(IDEA)及MISTY(KASUMI)结构算法在RAMCA上的映射过程.在65nm CMOS工艺下完成了逻辑综合和功能仿真.实验表明,RAMCA工作频率可达到1GHz,面积约为1.13mm2,消除工艺影响后,对各分组密码算法的运算速度均高于现有专用指令处理器以及Celator、RCPA和BCORE等阵列结构密码处理系统.Among the existing reconfigurable block cipher hardware structures, the special instruction processor does not achieve high throughput rate, while resource utilization of the reconfigurable block cipher processing array is low and mapping process is very complicated. Therefore, the reconfigurable asymmetrical multi-core architecture （RAMCA） for block cipher was designed. Mapping processes of typical structures, which were SP （AES-128） ,Feistel （SMS4）, L-M （I- DEA） and MISTY （KASUMI）,was analyzed. Hardware implementation was designed and synthesized in a 65nm CMOS process. The experimental area is about 1.13sq mm while frequency reaches 1GHz. After the influence of the process is eliminated, the performance of RAMCA is higher than that of other special instruction processors and most of the reconfigurable block cipher processing arrays, such as Celator, RCPA, BCORE, etc.

关 键 词：分组密码 异构多核 可重构 并行处理 密码处理器 

分 类 号：TN492[电子电信—微电子学与固体电子学]