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作 者:姚睿[1] 何坤[1] 朱萍[1] 李增武[1] 羊宇中
机构地区:[1]南京航空航天大学自动化学院,江苏南京210016
出 处:《国防科技大学学报》2017年第3期69-76,共8页Journal of National University of Defense Technology
基 金:国家自然科学基金资助项目(61402226);中央高校基本科研业务费专项资金资助项目(NS2014036)
摘 要:利用位流重定位与差异配置技术对现有基于动态部分重构的演化硬件实现方法进行改进,以解决其演化复杂电路时位流存储开销大和演化速度慢的问题。利用Xilinx早期获取部分重构技术,定制能实现位流重定位的可演化IP核。原始位流文件经设计形成算子核位流库存于外部CF卡上,方便系统调用。将现场可编程门阵列片内软核处理器Micro Blaze作为演化控制器,采用染色体差异配置技术,在线实时调节可演化IP核的电路结构,构成基于片上可编程系统的自演化系统。以图像滤波器的在线演化设计为例,在Virtex-5现场可编程门阵列开发板ML507上对系统结构和演化机制进行验证,结果表明,所提演化机制能有效节省位流存储空间,提高演化速度。To break through the limitations of huge memory space and low evolution speed for complex circuits′ evolution, the bitstream relocation and the discrepancy configuration were adopted to improve the efficiency of the evolvable hardware implementation approach based on dynamic partial reconfiguration. Firstly, an evolvable IP core capable of bitstream relocation was customized by using the technology of early stage accession to partial reconfiguration provided by Xilinx. Then the original bitstream files were presynthesized to form a partial bitstreams library stored in the CF memory for the system to call. Next, a self-evolving system based on a programmable chip system was built, in which the soft processor, MicroBlaze, was utilized as the evolution controller. And the discrepancy configuration was adopted for the real-time adjustment of the circuit topology of the evolvable IP core. Finally, the system structure and the self-evolving mechanisms were verified by the online evolution of digital image filters implemented on the Xilinx Virtex-5 FPGA(field programmable gate array) development board ML507. Experimental results show that the proposed evolutionary mechanisms can reduce the storage space of bitstream files and can accelerate the speed of evolution significantly.
关 键 词:演化硬件 现场可编程门阵列 位流重定位 差异配置 自演化
分 类 号:TP302[自动化与计算机技术—计算机系统结构]
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