High holding voltage SCR for robust electrostatic discharge protection  

作　　者：齐钊 乔明 何逸涛 张波 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China

出　　处：《Chinese Physics B》2017年第7期346-351,共6页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Grant Nos.61376080 and 61674027);the Natural Science Foundation of Guangdong Province,China(Grant Nos.2014A030313736 and 2016A030311022)

摘　　要：A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

关 键 词：electrostatic discharge holding voltage latch-up-free failure current 

分 类 号：TN34[电子电信—物理电子学]