A high-accuracy DCO with hybrid architecture  

作　　者：Yapeng Sun Huidong Zhao Shushan Qiao Yong Hei Fuhai Zhang 

机构地区：[1]Collage of Electronic Information and Optical Engineering, Nankai University [2]Institute of Microelectronics, Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2017年第7期111-116,共6页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.61306025,61474135)

摘　　要：In this paper, a novel hybrid digital-controlled oscillator（DCO） is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts： DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature（PVT） variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm^2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80℃ temperature variations in TT, FF,SS corners.In this paper, a novel hybrid digital-controlled oscillator（DCO） is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts： DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature（PVT） variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm^2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80℃ temperature variations in TT, FF,SS corners.

关 键 词：high accuracy DCO all-digital PVT variations 

分 类 号：TN752[电子电信—电路与系统] TU398[建筑科学—结构工程]