基于加速度计产品的ASIC版图设计和验证  

ASIC Layout Design and Verification based on Accelerometer

作　　者：李侠 王浩 LI Xia WANG Hao(CSMC Technologies Corporation Shanghai Design Service, Shanghai 201103, China)

机构地区：[1]无锡华润上华半导体有限公司上海分公司,上海201103

出　　处：《中国集成电路》2017年第7期42-48,58,共8页China lntegrated Circuit

摘　　要：ASIC(Application Specific Integrated Circuit),是一种为了专门目的而设计的集成电路。ASIC版图设计是把ASIC电路物理实现,称为集成电路后端设计。本文通过一款加速度计芯片设计,介绍ASIC版图设计和验证流程。从版图布局开始,包括输入输出端口IO(Input Output)的选用,模拟模块的全定制版图设计,数字模块的自动布局布线版图设计。ASIC is the abbreviation of Application Specific Integrated Circuit. It is a kind of integrated circuit design for a specific purpose. ASIC layout design is IC back-end design that convert the circuit to physical layers. This explains the ASIC layout design and verification flow base on Accelerometer, begin from layout floor plan, inc IO＇ s choice and analog full-custom layout design and digital APR layout design. paper luding

关 键 词：加速度计 模拟版图设计 数字版图设计 版图验证 

分 类 号：TN402[电子电信—微电子学与固体电子学]