面向超高清应用的并行解码处理器设计  

The Design of Parallel Decoder Aiming at Ultra High Definitlon Application

作　　者：韩学森[1] 张德学[1] 张存生[1] 王超 冀贞贤 杜飞飞[1] HAN Xue-sen ZHANG De-xue ZHANG Cun-sheng WANG Chao JI Zhen-xian DU Fei-fei(College of Electronic, Communication and Physics, Shandong University of Science and Technology, Qingdao 266590, Chin)

机构地区：[1]山东科技大学电子通信与物理学院,山东青岛266590

出　　处：《中国集成电路》2017年第7期49-53,共5页China lntegrated Circuit

摘　　要：本设计在对称多处理器架构的工作站上对面向超高清HEVC(High Efficiency Video Coding,高效视频编码)应用的并行解码处理器进行研究。设计了一种负载稳定且扩展能力强的并行解码器系统架构,在对解码过程的计算复杂度进行统计的基础上,将任务划分到各个模块分别执行,并通过OOP(Object-oriented programming,面向对象的程序设计思想)进行实现。然后采用视频编码联合组官方测试标准对并行解码处理器进行性能测试,证实其在超高清应用解码中所具有的实时性能。This design explores the real-time decoding parallel processor for ultra high definition HEVC ＂High Effi- ciency Video Coding （ HEVC ） ＂ video on a symmetric muhiprocessing platform. This paper designs a parallel de- coder system architecture with stable load and strong expansibility. Based on the calculation of the computational complexity of the decoding process, the tasks are divided into modules and implemented by OOP （ Object Orienting programming ）. Finally, the performance of the processor is tested according to the test method adopted in the stan- dard, which realizes the real-time performance in the ultra-high-definition video decoding.

关 键 词：超高清 HEVC 实时解码 并行化 

分 类 号：TN919.81[电子电信—通信与信息系统]