一种处理器体系结构级功耗评估工具设计  

Design of An Architectural Level Power Estimation Tool for Processors

作　　者：刘志宏[1] 张星[1] 张洪峰[1] 

机构地区：[1]武汉第二船舶设计研究所,武汉430064

出　　处：《舰船电子工程》2017年第7期175-179,共5页Ship Electronic Engineering

摘　　要：体系结构级功耗评估能让设计者在设计前期对处理器进行架构权衡,极大地减少设计开销。论文从体系结构级、电路级和工艺级三个层次,结合工艺缩放比例原理和RTL反馈建模方法,进行处理器功耗建模;在功耗模型基础上,实现体系结构级功耗评估工具的设计;通过速度、精度分析,表明该体系结构级功耗评估工具在极大提升了功耗评估速度的前提下保证了功耗评估精度。Power estimation at architectural level provides the designer with more flexibility to trade off power with speed and area in the early stage of design procedure, and also greatly reduces design cost. In the paper, power models are designed at archi-tecture-level, circuit-level and technology-level, both the technology scaling theory and the RTL backwards modeling method are used. Based on the power models, the architectural level power estimation tool is designed. At last,an analysis of the estimation tool’s performance is given from the respect of accuracy and speed,the architectural level power estimation tool speeds up a lot while ensuring the estimation accuracy.

关 键 词：体系结构级 功耗模型 功耗评估 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]