一种高速跳频信号接收架构设计  

Architecture Design of High-speed Frequency-Hopping Receiver

作　　者：夏明赟[1] 

机构地区：[1]中国电子科技集团第三十研究所,四川成都610041

出　　处：《通信技术》2017年第7期1375-1380,共6页Communications Technology

摘　　要：跳频是战场通信中广泛应用的一种抗截获、抗干扰技术,目前朝着宽频段、高跳速等方向发展。它的信号在时域上持续时间短,频域上则呈现瞬时窄带、长时宽带的特点。因此,在非合作条件下,对于普通的扫频式接收、模拟信道化接收等类型接收机,它已难以高效实现对其的全概率接收捕获。针对这一情况,根据实际项目需要,针对108~512 MHz范围内2 000跳的高速跳频信号,设计了一种模拟信道化结合多级数字信道化的架构,降低了硬件资源规模,同时保证了对信号的全概率接收。Frequency hopping as an anti-interception and anti-jamming technique, is widely used in battlefield communications, and now, develops towards broadband, high speed and so on. In time domain, its signal duration is short, while in frequency domain, it exhibits the characteristics of instantaneous narrow band and long-time broadband. For this reason, and under non-cooperative conditions, frequency hopping can hardly achieve full-probability receiver acquisition for conventional sweeping, receiving and analog channelized receivers. In view of this situation, based on the actual needs of the project, and aiming at high-speed channelized frequency-opping signal with 2000 hops in the range of 108 ~ 512 MHz, the architecture in combination of analog channelization with multi-level digital channelization is designed and implemented, thus reducing the size of hardware resource, while ensuring the full probability receiving of the signal.

关 键 词：跳频 数字信道化 多相滤波 带通采样 

分 类 号：TN858[电子电信—信息与通信工程]