一种可重构计算系统的微架构设计与实现  

Design and Implementation of Micro Architecture for Reconfigurable Computing System

作　　者：柴镇 柴志雷[1,2] 吴东 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]数字工程与先进计算国家重点实验室,江苏无锡214125

出　　处：《微电子学与计算机》2017年第8期33-37,共5页Microelectronics & Computer

基　　金：数学工程与先进计算国家重点实验室开发基金(2015A07)

摘　　要：为了推动FPGA计算的大规模应用,设计并实现了一种基于动态部分可重构机制的FPGA计算系统微架构.该架构提供了一套提升FPGA开发效率的用户开发模式,可在FPGA中支持SIMD/MIMD并行计算模式,并通过可重构计算单元的通信支持流水计算模式.实验结果表明,该架构在保持FPGA计算系统高性能、低功耗优势的同时,可有效地简化用户的编程模式.In order to promote the large-scale application of FPGA computation, a micro architecture of FPGA based on dynamic partial reconfiguration mechanism is designed and implemented. The architecture provides a set of user- development mode that can improve the development efficiency of FPGA, which can support SIMD/MIMD parallel computing mode in FPGA, and supports pipeline mode through communication of reconfigurable units. The experimental results show that the architecture can effectively simplify the user＇ s programming mode while maintaining the high performance and low power consumption of FPGA computing system.

关 键 词：可重构计算 动态部分可重构 编程模式 FPGA 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]