Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process  

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

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作  者:王艳蓉 杨红 徐昊 罗维春 祁路伟 张淑祥 王文武 闫江 朱慧珑 赵超 陈大鹏 叶甜春 

机构地区:[1]Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics,Chinese Academy of Sciences,Beijing 100029,China [2]North China University of Technology,Beijing 100144,China [3]University of Chinese Academy of Sciences,Beijing 100049,China

出  处:《Chinese Physics B》2017年第8期407-410,共4页中国物理B(英文版)

基  金:supported by the National High Technology Research and Development Program of China(Grant No.2015AA016501);the National Natural Science Foundation of China(Grant No.61306129)

摘  要:In the process of high-k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.In the process of high-k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

关 键 词:high-k/metal gate multi deposition multi annealing stress-induced leakage current post deposi-tion annealing 

分 类 号:TN386[电子电信—物理电子学]

 

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