一种S波段跳频源的设计  

A Method of Designing S-Band Hopping Frequency Synthesizer

作　　者：刘玲玲[1] 王自力[1] 葛枫[1] 孙婷婷[1] 

机构地区：[1]中国电子科技集团第十六研究所,合肥230043

出　　处：《电子器件》2017年第3期588-592,共5页Chinese Journal of Electron Devices

摘　　要：为某项目设计一款频率在2 GHz^3 GHz宽带跳频源,频率间隔为1 MHz,跳频点数为1 001点。该跳频源要求相位噪声小于-100 dBc@1 kHz,杂散优于60 dB。分析指标和软件仿真计算,采用HITTITE公司的HMC830锁相芯片来实现该设计方案。采用HITTITE公司的PLL仿真设计软件对环路滤波器进行优化设计后应用到实际电路中,使得该芯片在-55℃到+85℃均可稳定工作。通过外接串口通信控制模块,实现频率的跳变。最终该设计的实物测试相位噪声、杂散指标均优于目标值。测试得到该频率源相位噪声可达到-100 dBc/Hz@1 kHz,杂散指标能够达到-70 dB。Design a 2 GHz^3 GHz hopping frequency synthesizer,frequency spacing 1 MHz,frequency hopping points to 1 001 points.The hoping frequency synthesizer requires phase noise less than-100 dBc@1 kHz,and Spur is better than 60 dB.The design is achieved using HITTITE’s HMC830 chip phase-locked after Software simulation and analysis of indicators.The design has been applied to the actual circuit by using HITTITE’s PLL loop filter simulating design software to optimize the rear design.The chip can be stable at-55℃to＋85℃.Through the external serial communication control module hoping is realized.Phase noise,spurious performance of the final design are better than the target value.Experimental results show that the phase noise is-100 dBc/Hz@1 kHz and spurious is-70 dB of Engineering application value.

关 键 词：频率源 频率跳变 锁相环 杂散 

分 类 号：TN741[电子电信—电路与系统]