一种带斩波的双采样Σ-Δ调制器  

A Double Sampling Σ-Δ Modulator with Chopper

作　　者：田也[1,2] 陆序长 谢亮[1,2] 金湘亮[1,2] 

机构地区：[1]湘潭大学物理与光电工程学院,湖南湘潭411105 [2]微光电与系统集成湖南省工程实验室,湖南湘潭411105

出　　处：《微电子学》2017年第4期445-450,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61274043);国家自然科学基金重点项目(61233010);湖南省自然科学杰出青年基金资助项目(2015JJ1014)

摘　　要：设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 d B,THD为-104.9 d B,ENOB可达16.78位,总功耗仅为0.4 m A。A fully-differential capacitive isolation Σ-Δ modulator suitable for ultra-high magnetic field immunity was designed. A one-bit quantized second-order single-loop feed-forward topology（ CIFF） was applied. The low frequency noise and the offset voltage were decreased by the chopper technology. Compared with the conventional fully-differential structure,four sampling capacitances were used in each stage of integrator. It meant that the integrator achieved sample and integral twice a clock cycle. Therefore,the required external clock frequency of this integrator was only one half that of the traditional integrator＇s. The design requirements of SR and GBW of the op-amp were also reduced,which meant that the design of low power became true. The circuit was designed and simulated in the CSMC 0. 35 μm CMOS technique under the circumstances of a sampling frequency of 10 MHz,an oversampling rate of 256 and a supply voltage of 5 V. The post simulation results showed that the modulator achieved a SNDR of 100. 7 d B,a THD of 104. 9 d B,and an ENOB of 16. 78.The total circuit power consumption was only 0. 4 m A.

关 键 词：Σ-Δ调制器 双采样前馈积分器 斩波技术 

分 类 号：TN761[电子电信—电路与系统]