基于MIPS指令集的流水线CPU设计与实现  

Design and Implementation of Pipeline CPU Based on MIPS Instruction Set

作　　者：刘秋菊 张光照[2] 王仲英[2] 

机构地区：[1]郑州工程技术学院信息工程学院,郑州450000 [2]河南经贸职业学院技术科学系,郑州450018

出　　处：《实验室研究与探索》2017年第8期148-152,172,共6页Research and Exploration In Laboratory

基　　金：河南省科技攻关项目(172102210606);河南省高等学校重点科研项目(17B520040)

摘　　要：提出了一种CPU设计方案,实现指令集为MIPS指令集中选取15条指令作为本CPU的基本指令,采用基本5步流水线CPU设计。分析了流水线CPU的逻辑结构与指令的处理过程,给出了取指阶段IF、译码阶段ID、执行阶段EX、内存访问阶段MEM、寄存器写回阶段WB阶段的设计与实现。对流水线产生的相关性问题,采用Bubble法和Forwarding法相结合的方法来消除相关性,在FPGA平台上进行了测试,测试结果表明,该方案符合设计要求。In this paper,a design method of CPU was proposed,the instruction set of the CPU contained 15 items of MIPS instruction set,and the basic method of five step pipeline CPU design was used. Analyses were conducted on the logic structure of the pipeline CPU and the processing of the instruction. This paper also gave design and realization of stage IF,stage ID,stage EX,stage MEM and stage WB. About the pipeline-related problems,the paper adopted Bubble and Forwarding technologies to eliminate it. The tests on the FPGA platform show that the scheme meets the design requirements.

关 键 词：流水线 中央处理器 设计 指令集 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]