高速四相时钟电路设计  

Design of High Speed Four-Phase Clock Generation Circuit

作　　者：刘勇聪 王建业[1] 王海龙 LIU Yong-eong WANG Jian-ye WANG Hai-long(Air and Missile Defense Academy, Air Force Engineering University, Xi＇ an 710051, China)

机构地区：[1]空军工程大学射频及高速数字组件实验室,陕西西安710051

出　　处：《测控技术》2017年第9期142-144,150,共4页Measurement & Control Technology

摘　　要：基于IHP 130 nm SiGe BiCMOS工艺,设计了一个由基于RC网络相移特性的polyphase移相器和差分时钟缓冲器组成的2 GHz四相时钟电路。因单阶polyphase带宽不足而设计了三阶polyphase级联提高带宽。采用HBT(heterojuntion bipolar transistor)差分时钟缓冲取代MOS(metal oxide semiconductor)单端时钟缓冲,实现更高时钟频率的同时,差分结构也能有效抑制流入采样电容的时钟信号馈通。各模块版图设计均采用高度对称结构来消除相位误差。仿真结果表明,差分输入2 GHz正弦波时,可输出4路相位相差90°方波时钟信号,时钟上升时间约15 ps,4路时钟相位误差小于2.2°,应用到4通道采样保持电路后可成功采样和保持8 GHz正弦输入信号。Based on the IHP 130 nm SiGe BiCMOS process, a four-phase 2 GHz clock generation circuit is de- signed, which consists of a polyphase phase shifter applying phase shift character of RC network and a differen- tial clock buffer. A third-order cascade polyphase structure is designed to broaden the bandwidth of single stage polyphase circuit. HBT differential clock buffer also replaces single-ended MOS clock buffer to realize higher clock frequency. At the same time, differential structure can effectively inhibit clock signal feed-through which would flow into sampling capacitance. The layout of every block is designed to eliminate phase errors by using a highly symmetrical structure. Simulation results show that four channel clock square-wave signal, whose difference of phase is 90°, and could be generated when differentially inputting 2 GHz sinusoidal signal. The rising time of proposed clock is about 15 ps, and the phase error between different clocks is less than 2.2°. 8 GHz sinusoidal input signal could be successfully tracked and held when applying the proposed clock into a four-channel track and hold amplifier.

关 键 词：RC网络 POLYPHASE 差分时钟缓冲 时钟信号馈通 

分 类 号：TN453[电子电信—微电子学与固体电子学]