BESⅢ主漂移室内室升级MAPS芯片探针台测试系统设计  

Probe Testing System of MAPS Chips for the BESⅢ Inner Drift Chamber Upgrade

作　　者：周传兴 董明义[1,2,3] 鞠旭东 董静[1,2] 欧阳群 

机构地区：[1]核探测与核电子学国家重点实验室,北京100049 [2]中国科学院高能物理研究所,北京100049 [3]中国科学院大学,北京100049

出　　处：《核电子学与探测技术》2017年第3期225-230,共6页Nuclear Electronics & Detection Technology

基　　金：国家自然科学基金(U1232202)资助

摘　　要：为满足北京谱仪Ⅲ主漂移室内室升级MAPS芯片测试需要,设计了一套用于芯片功能检查的芯片探针台测试系统。该系统实现了批量芯片JTAG通讯、芯片功耗、像素箝位电压、读出数据等芯片的功能检查,并可以进行芯片噪声水平以及甄别器阈值扫描等初步测试。芯片的探针台测试不仅在非邦定的情况下完成了芯片的筛选,同时可为后续芯片在探测器上工作时的阈值等参数配置提供参考。To meet the requirement of the chip test for a MAPS detector prototype, which is one of the BES Ⅲ inner drift chamber upgrade schemes, a probe testing system was set up for the chip functional verification and preliminary performance test. With this system, the JTAG communication, the power consumption and the clamping voltage of the chips were tested, as well as the data format and chip output. What＇s more, the noise level test of the chips and the threshold scan of the discriminators were carried out. The test results not only help to select the good chips for the construction of the detector prototype,but also can provide a reference for the parameter configuration of the chips when they are working in the detector.

关 键 词：单片型有源像素芯片 硅像素探测器 探针卡 芯片探针台测试 

分 类 号：TL814[核科学技术—核技术及应用]