低电压超低功耗人工耳蜗植入体芯片设计  

Design of low voltage,ultra low-power cochlear implanted chip

作　　者：陈黎明 陈铖颖 袁甲[2] 杨骏[2] 

机构地区：[1]厦门理工学院光电与通信工程学院,福建厦门361024 [2]中国科学院微电子研究所,北京100029

出　　处：《华中科技大学学报（自然科学版）》2017年第9期1-5,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目(61306093)

摘　　要：基于台积电TSMC 0.35μm 3.3V标准半导体工艺,完成一款低电压、超低功耗人工耳蜗植入体芯片设计与流片.首先,基于目标工艺设计一套2.0V低电压标准单元库,完成电路结构设计、特征化提取和版图设计;其次,以2.0V低电压标准单元库为目标工艺库,完成植入体芯片综合及物理设计,引入基于蒙特卡罗仿真的统计静态时序分析方法,提高低电压路径的时序收敛性.测试结果显示:当工作电压由3.3V降至2.0V时,人工耳蜗植入体芯片功能正常,全芯片功耗下降了74.7%.Based on TSMC （Taiwan Semiconductor Manufactory Company）0.35μm 3.3 V standard CMOS （complementary metal oxide semiconductor）technology,a low voltage,ultra low-power co-chlear implanted chip was developed.First,a set of 2.0 V low voltage standard cell was implemented, including circuit architecture,timing characteristic and layout.Then,the low voltage cochlear im-planted chip was designed,using the 2.0 V standard cells as target library.For the convergence of timing paths,a novel SSTA （statistical static timing analysis）method was introduced,employing Monte Carlo simulation.The test results indicate that cochlear implanted chip reduces the power con-sumption by 74.7% when power supply drops from 3.3 V to 2.0 V.

关 键 词：人工耳蜗 低电压 超低功耗 统计静态时序分析 超大规模集成电路(VLSI) 

分 类 号：TN47[电子电信—微电子学与固体电子学]