基于CSMC 0.5微米混合信号工艺的ESD保护电路实现  

Implementation of the ESD Protection Circuit Based on CSMC 0.5 Micron Mixed Signal Process

作　　者：李湘君 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2017年第5期8-11,共4页Microprocessors

摘　　要：ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,MOS器件的栅氧化层面积小、厚度薄,因此在测试、封装和应用过程中,来自人体或设备的静电电荷可产生的高达几千伏以上的电压,足以使栅氧化层击穿,造成器件失效。根据选用的CSMC 0.5μm FEOL 0.35μm BEOL_Mixed_Signal工艺推荐的ESD保护结构,完成输入级、输出级及电源地的ESD电路设计,同时根据版图设计规则,完成了芯片端口ESD设计。ESD protection circuit has become an integral part of CMOS integrated circuit.MOS device gate oxide area is small,and the layer thickness is thin,therefore in the process of testing,packing and application,electrostatic charge from the human body or equipment can produce as much as more than a few kV voltage enough to make the gate oxide breakdown,and cause device failure[1].According to the ESD protection structure recommended by the selected CSMC 0.5μm FEOL_0.35μm BEOL_Mixed_Signal process,the ESD circuit of input level,output level and power ground is designed,meanwhile,the design of the chip port ESD is also achieved according to the design rules of the layout.

关 键 词：ESD保护电路 输入级电路设计 输出级电路设计 电源地电路设计 版图设计 混合信号工艺 

分 类 号：TN306[电子电信—物理电子学]