一种无源植入式神经刺激器中模拟前端的设计  

Design of Analog Front-End in a Passive Implantable Neural Stimulator

作　　者：王宇辰[1] 彭晓宏[1] 侯立刚[1] 耿淑琴[1] WANG Yuchen PENG Xiaohong HOU Ligang GENG Shuqin(VLSI ＆ System Lab, Beijing University of Technology, Beijing 100124, P. R. China)

机构地区：[1]北京工业大学集成电路与系统集成实验室,北京100124

出　　处：《微电子学》2017年第5期620-624,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60976028);北京市自然科学基金资助项目(4152004)

摘　　要：设计了一种可应用于超高频无源植入式神经刺激器的模拟前端电路。对无源植入式芯片模拟前端的系统架构进行了论述,简述了前端架构中各个模块的工作原理,通过优化系统结构,减小了系统复杂度和版图面积。模块包括整流电路、电源管理电路、调制解调电路、上电复位电路和时钟产生电路。其中,整流电路工作时,效率可达到45%以上,并且能提供两种不同的工作电压。使用Cadence Spectre对设计电路进行仿真,并通过TSMC 0.35μm BCD工艺进行流片验证。结果显示,该模拟前端的直流功耗为0.06mW,芯片面积为0.4mm^2,可以满足植入式神经刺激器的要求。An analog front-end circuit applicable to ultra-high frequency passive implantable neural stimulators was designed.The system architecture of the passive front-end analog chip was discussed,and the circuit principle of each module in the front-end architecture was described.The system complexity and layout area were reduced by optimizing the system structure.The system comprised modules of rectifier circuit,power management circuit,modulation and demodulation circuit,power on reset circuit and clock generating circuit.The rectifier circuit had an operating efficiency of more than 45%,and provided two different operating voltages.The proposed circuit was simulated by Cadence Specter.It was taped out and verified in the TSMC 0.35μm BCD process.The simulation results showed that the power consumption of the analog front-end was 0.06 mW,and the chip area was 0.4 mm^2.The performances of the analog front-end circuit could meet the requirements of implanted neural stimulators.

关 键 词：模拟前端 无源植入式装置 超高频 模拟集成电路 

分 类 号：TN433[电子电信—微电子学与固体电子学]