一种用于E1接口的全数字锁相环  

An All Digital Phase Locked Loop for E1 Interface

作　　者：许家榆 黄启俊[1] 罗将[1] 王豪[1] 常胜[1] 何进[1] XU Jiayu HUANG Qijun LUO Jiang WANG Hao CHANG Sheng HE Jin(School of Physics and Technology, Wuhan University, Wuhan 430072, P. R. Chin)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072

出　　处：《微电子学》2017年第5期658-661,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61204096;61404094);中国博士后科学基金资助项目(2012T50688);中央高校基本科研项目(2042015kf0174;2042014kf0238);湖北省自然科学基金资助项目(2014CFB694);江苏省科学基金资助项目(BK20141218)

摘　　要：提出了一种从E1信号中提取时钟的全数字锁相环。该锁相环结构简单、易于实现、可靠性高,提取的时钟信号的抖动和漂移均满足ITU-T G.823的要求。建立了相位传递数学模型,对电路的原理进行了分析。对该锁相环进行了实验验证,结果表明,在满足ITU-T相关建议的情况下,该电路完全可以从E1信号中提取时钟。An all digital phase locked loop（ADPLL）which was used to recover the clock from E1 signal was proposed.This ADPLL featured simple structure and high reliability.It was easy to implement.Both the jitter and drift of the recovered clock signal could meet the requirements of ITU-T G.823.The mathematical model of phase transfer was established to analyze the principle of the proposed circuit.The phase locked loop was verified experimentally.Results showed that the clock could be recovered from E1 signal while the relevant recommendations of ITU-T was satisfied.

关 键 词：E1接口 全数字锁相环 FPGA 序列滤波器 数控振荡 

分 类 号：TN911[电子电信—通信与信息系统]