一种宽频带低抖动锁相环  

A Wide Tuning Range and Low Jitter Phase-Locked Loop

作　　者：刘辉华[1,2] 李平 李磊[3] 徐小良[3] 张宪[3] LIU Huihua LI Ping LI Lei XU Xiaoliang ZHANG Xian(School of Microelec. and Sol. Sta. Elec. , University of Electronic Science and Technology of China, Chengdu 611731, P. R. China School of Elec. Engineer. , University of Electronic Science and Technology of China, Chengdu 611731, P. R. China Institute of Sci. and Technol. of Elec. , University of Electronic Science and Technology of China, Chengdu 611731, P. R. China)

机构地区：[1]电子科技大学微电子与固体电子学院,成都611731 [2]电子科技大学电子工程学院,成都611731 [3]电子科技大学电子科学技术研究院,成都611731

出　　处：《微电子学》2017年第5期662-665,共4页Microelectronics

基　　金：国家自然科学基金资助项目(U1630133)

摘　　要：详细分析了自偏置锁相环(PLL)的工作原理,采用一种新颖的折叠式电荷泵(CP)结构,包含一个宽摆幅电流镜,实现了更好的电流匹配,降低了PLL的系统抖动。该PLL采用130nm CMOS工艺进行制造。VCO的调频范围为0.43~1.54GHz。在1.25GHz工作频率下,频偏1 MHz处,PLL的相位噪声为-89.6dBc/Hz,均值抖动为3.03ps,峰峰值抖动为18.16ps,芯片面积仅为0.34mm2。The operating principle of self-bias phase-locked loop（PLL）was analyzed in detail.A novel folded charge pump（CP）including a wide-swing current mirror was implemented to improve the current matching,which had reduced the jitter of the PLL.The PLL was fabricated in a 130 nm CMOS process.The VCO achieved a wide tuning range from 430 MHz to 1.54 GHz.At the operating frequency of 1.25 GHz,the phase noise of the VCO at 1 MHz offset was only -89.6 dBc/Hz.The PLL＇s RMS jitter was 3.03 ps,and the peak-to-peak jitter was 18.16 ps.The chip＇s area was only 0.34 mm^2.

关 键 词：锁相环 自偏置 电荷泵 

分 类 号：TN432[电子电信—微电子学与固体电子学]