一种低参考杂散高PSNR的Ⅰ型锁相环  

A Type-Ⅰ Phase-Locked Loop with Low Reference Spur and High Power Supply-Noise Rejection Ratio

作　　者：席娜 张吉利[1] 叶棪 林福江[1] XI Na ZHANG Jili YE Yan LIN Fujiang(Micro-Nano Electronic System Integration Center, University of Science and Technology of China, Hefei 230026, P. R. Chin)

机构地区：[1]中国科学技术大学微纳电子系统集成研究中心,合肥230026

出　　处：《微电子学》2017年第5期666-669,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61404123)

摘　　要：基于GF 130nm CMOS工艺,设计了一种低参考杂散、高电源噪声抑制比(PSNR)的Ⅰ型锁相环。相较于电荷泵型锁相环,Ⅰ型锁相环存在锁定范围小、参考杂散性能差等缺点。此外,压控振荡器是对电源噪声敏感的模拟电路,电源线上的噪声会恶化振荡器的输出抖动性能。通过引入采样保持电路和电源电压整形器,降低了Ⅰ型锁相环的参考杂散和电源噪声敏感系数。仿真结果表明,设计的I型锁相环的工作频率范围为2.1~2.8GHz,参考杂散为-66dBc,PSNR为-25dB,功耗为10mW,芯片占用面积为0.009mm2。Based on GF 130 nm CMOS process,a high power supply-noise rejection ration and low reference spur type-Ⅰ PLL was designed.Compared with the charge pump phase-locked loop,the type-Ⅰ PLL had the disadvantages of small lock range and worse reference spur.In addition,the ring voltage controlled oscillator was analog circuit,and it was sensitive to the power supply noise.Noise in power line would deteriorate the oscillator output jitter performance.The reference spur and the power supply noise sensitive coefficient of the type-Ⅰ PLL had been reduced by employing a sample-hold circuit and a power supply voltage regulator.The simulation results showed that the proposed type-Ⅰ PLL could operate at a frequency range of 2.0-2.8 GHz.The reference spur was -66 dBc,and the power supply-noise rejection ratio（PSNR）was -24 dB while it consumed 9.7 mW from a 1.5 V supply.It occupied 0.009 mm^2.

关 键 词：Ⅰ型锁相环 参考杂散 电源噪声 CMOS集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]