基于FPGA的CAVLC解码器设计  

A design of CAVLC decoder based on FPGA

作　　者：马雨然 任超伟[1] 张文明[1] MA Yu-ran REN Chao-wei ZHANG Wen-ruing(Institute of Optics and Electronics, Chinese Academy of Sciences, Chengdu 610209, China)

机构地区：[1]中国科学院光电技术研究所,四川成都610209

出　　处：《电子设计工程》2017年第21期120-124,共5页Electronic Design Engineering

摘　　要：为了提高H.264解码器中基于上下文的自适应变长CAVLC解码器的查表速度,本文给出了一种基于FPGA的CAVLC解码工程解决方案。首先在同一码表中根据码字前缀0的个数对码表进行分组,减小查表的遍历深度。分组后再采用根据后缀计算查表,减少条件判断的次数,以提高查表速度。结果表明,该设计满足1080P@30fs的视频实时解码要求。In order to speed up the table lookup of Context-based Adaptive Variable LengthCoding in H.264 decoder, this paper proposes a new engineering solution of CAVLC decoder based on FPGA. The basic idea is to group a table according to the numbers of zero in code prefix, so to reduce the traversal depth of the table. After grouping, using the code suffix to calculate the parameter of decoder, it reduces the times of condition judgment and gets the decoded output quickly. The results show that the design could support the real-time decoding of 1080P@3Ofs high definition video.

关 键 词：H.264 CAVLC 码表分组 FPGA 

分 类 号：TN941.1[电子电信—信号与信息处理]