可重构视频阵列处理器中全局控制器的设计与实现  

The Design and Implementation of Global Controller in Reconfigurable Video Array Processor

作　　者：张雪婷 蒋林 邓军勇 吕青 武鑫 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《微电子学与计算机》2017年第11期75-79,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(61272120;61634004;61602377);陕西省自然科学基金资助项目(2015JM6326);陕西省科技统筹创新工程项目(2016KTZDGY02-04-02)

摘　　要：提出了一种基于可重构阵列处理器的视频编解码方案,重点描述面向算法切换与资源调整的全局控制器设计方法,通过层次化编程网络将阵列处理器与主机接口相连,从而实现对视频阵列处理器计算资源的控制与管理.实验结果表明,该全局控制器支持多种模式的指令加载以及计算数据的反馈,在现场可编程门阵列(Field Programmable Gate Array,FPGA)上最高工作频率可达539.96MHz,相较于同类型阵列结构,全局控制器的执行周期降低了50%.A video codec scheme based on reconfigurable array processor has been proposed.The design method of global controller for algorithms switching and resources adjustment is mainly described.In this design,array processors and host interface has been connected through hierarchical programming network to realize the control and management of computed resources for the video array processors.The experimental results shows that this global controller support various of modes to load instructions and feedback the calculated data.The maximum operating frequency in the field programmable gate array（FPGA）can up to 539.96 MHz and compared with the same type array structure,the execution cycle of global controller is reduced by 50%.

关 键 词：可重构 视频阵列处理器 全局控制器 层次化编程网络 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]