一款增益可调的28 nm三通道10位DAC  

A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process

作　　者：熊利伟 杜占坤[1] 刘珂[1] 马骁[1] 庞晓敏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《微电子学与计算机》2017年第11期89-93,共5页Microelectronics & Computer

基　　金：国家科技重大专项资助项目(Y4GZ242001)

摘　　要：基于SMIC 28nm CMOS工艺,实现了一款增益可调的三通道的300MS/s 10bit的数模转换器.此数模转化器可以通过5位的控制字实现0^-5.75dB的增益调节,适应更多的应用环境.数模转换器采用分段式结构,其中高六位采用温度计码,低四位采用二进制码.在电流源单元开关部分采用限幅电路,提高无杂散动态范围.带隙基准单元采用低电压输出结构,满足电压电流转换单元中的栅压要求.在1.8V模拟电源电压,1.05V数字电压下,采样时钟在300 MHz的时候,无杂散动态范围(SFDR)为64dB,微分非线性小于(DNL)±0.3LSB;积分非线性小于(INL)±0.4LSB.This paper presents a variable gain three-channel 10-bit current steering CMOS digital-to-analog converter（DAC）implemented in a standard 28-nm CMOS technology.The DAC achieved variable gain of 0^-5.75 dB with five-bits control words to apply to a wider range of applications.The DAC is segmented as 6＋4,where the 4-LSB bits are implemented in binary and the 6-MSB bits are implemented in unary architecture.The spurious free dynamic range（SFDR）of this DAC can be improved by using clipper circuit in the part of switches.The reference voltage of bandgap must be low enough to meet the requirements of bias voltage in the part of voltage changing to current.The circuit is fabricated in 1.8-V analog power supply and 1.05-V digital power supply.For sampling frequencies up to300 MSample/s,the SFDR is better than 64 dB.The measured differential nonlinearity and integral nonlinearity are0.3 least significant bit（LSB）and 0.4 LSB,respectively.

关 键 词：DAC 数模转换器 电流舵 增益控制 

分 类 号：TN432[电子电信—微电子学与固体电子学]