一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器  

A 10-bit 2 Ms/S SAR ADC with Vcm-Based Switching Scheme

作　　者：刘滢浩 刘宏[1] 徐乐 田彤[1,2] 

机构地区：[1]中国科学院上海微系统与信息技术研究所,上海201801 [2]上海科技大学信息科学与技术学院,上海201210

出　　处：《微电子学与计算机》2017年第11期99-103,共5页Microelectronics & Computer

基　　金：上海市科委资金资助项目(14521106200);上海经信委资金资助项目(13XI-32)

摘　　要：针对无线传感网络中低功耗无线传感器的应用,设计了一种采样速率为16MSPS,精度10bit的全差分超低功耗逐次逼近型模数转换器(SAR ADC).提出一种基于Vcm-Based参考电压的开关切换逻辑,减少DAC模块参考电压开关切换的功耗.同时,DAC电容阵列模块采用分段式结构,单位电容采用优化的MOM电容,有效提高ADC的匹配性和精度;此外采用了双尾电流型动态锁存比较器,实现功耗的最优化.芯片采用CMOS 65nm工艺设计,后仿结果显示在1.2V电源电压及16MSPS采样率下,ADC有效位数达到9.42bit,功耗为140μW,品质因数(FOM)为12.8fJ/Conversion-step.Aiming at the application of low power wireless sensor in wireless sensor network,a ultra low power Successive Approximation Register Analog-to-Digital Converter（SAR ADC）has been designed.A switching logic based on Vcm-Based reference voltage is proposed to reduce the power consumption of the DAC when the reference voltage is switched.The DAC capacitor array module uses the sectional structure,the unit capacitance uses the optimized MOM capacitance,enhances the ADC matching and the precision effectively.In addition,a double tail current dynamic latch comparator is used to optimize the power consumption.The ADC is implemented in CMOS 65 nm technology.The post simulation results shown that under 1.2 Vsupply voltage,the sampling rate is 16 MSPS,the power consumption is 140μW,effective number of bits reached 9.42 bit,and the figure-of-merit（FOM）is 12.8 fJ/conversion-step.

关 键 词：逐次逼近型模数转换器 Vcm-Based 动态比较器 超低功耗 

分 类 号：TN4[电子电信—微电子学与固体电子学]