一种基于FPGA的多通道复用Viterbi译码器的设计与实现  

Design and Implementation of Multi-channel Multiplexed Viterbi Decoder Based on FPGA

作　　者：庞志锋 刘欣欣 王晓君 PANG Zhi-feng,LIU Xin-xin,WANG Xiao-jun（Hebei Umversity of Science ＆ Technology, Shijiazhuang 050000, China）

机构地区：河北科技大学信息科学与工程学院,河北石家庄050000

出　　处：《电脑知识与技术》2017年第10期251-253,共3页Computer Knowledge and Technology

摘　　要：卫星定位接收机中的卷积码译码即Viterbi译码,在处理器中面临着占有资源比较多、处理时间太长等问题,为了减少处理器中资源占用和提高它的处理速度,采用了多通道复用和串行加比选蝶形单元的方法,在FPGA平台上用硬件描述语言设计出一种高性能Viterbi译码器,大大减少资源占用,提高了接收机的处理速度。Satellite positioning receiver decoding convolutional code Viterbi decoder,facing the problem of share more resources and processing time in the processor,the processor in order to reduce the occupied resources and improve the processing speed,using multi channel multiplexing and serial plus selection butterfly unit method,using hardware description language to design a high performance Viterbi decoder FPGA platform,greatly reduce the resource utilization,improve the processing speed of the receiver.

关 键 词：卷积码 VITERBI算法 FPGA 资源占用 

分 类 号：TN919[电子电信—通信与信息系统;电子电信—信息与通信工程]