基于Kintex-7 FPGA的DDR3 SDRAM接口应用研究  

Application of DDR3 SDRAM interface based on Kintex-7 FPGA

作　　者：吴长瑞[1] 徐建清[1] 蒋景红[1] 

机构地区：[1]中国科学院声学研究所,北京100190

出　　处：《现代电子技术》2017年第24期21-24,27,共5页Modern Electronics Technique

基　　金：国家自然科学基金项目(11304343)

摘　　要：针对FPGA中使用DDR3进行大容量数据的缓存应用背景,采用模块化设计方法,提出基于Xilinx Kintex-7 FPGA的DDR3 SDRAM FIFO接口设计方案。在分析DDR3用户接口特点和用户接口时序的基础上,对不同读/写模式进行效率测试。借鉴标准FIFO的设计思想,结合DDR3 SDRAM控制器的特点,设计遍历状态机对该FIFO接口进行读/写测试。最后,原型机平台验证了该接口不仅具有标准FIFO简单易用的功能,而且具有存储空间大等优势。Aiming at the application background of using DDR3 for large-capacity data caching in FPGA, a design scheme of DDR3 SDRAM FIFO interface based on Xilinx Kintex-7 FPGA is presented according to the modularized design method. Based on the analysis of DDR3 user interface characteristics and user interface time sequence, the efficiency of different read- write modes was tested. In combination with the design thought of standard FIFO and characteristics of DDR3 SDRAM control- ler, the traversal state machine is designed to perform the read-wrlte test of the FIFO interface. The interface was verified with the prototype platform. The result demonstrates that the interface has the simple and easy-to-use functions of standard FIFO, and large storage space.

关 键 词：DDR3 SDRAM FIFO FPGA 遍历状态机 

分 类 号：TN43-34[电子电信—微电子学与固体电子学] TP332.3[自动化与计算机技术—计算机系统结构]