基于PLL倍频电路的设计与实现  

Design and implementation of frequency multiplier based on PLL

作　　者：杨坦[1,2] 廉吉庆 涂建辉 崔敬忠[1,2] 

机构地区：[1]兰州空间技术物理研究所,甘肃兰州730000 [2]真空技术与物理国防科技重点实验室,甘肃兰州730000

出　　处：《电子设计工程》2017年第23期105-108,112,共5页Electronic Design Engineering

摘　　要：锁相环由于其高集成度、良好的相位噪声和杂散特性,广泛的应用于通信、导航及遥测等领域。对于锁相环频率合成器,环路滤波器的设计对整个系统的性能起着决定性的影响。基于铷原子钟微波源的需求,文章利用锁相环技术设计了倍频电路。首先论述了锁相环的基本原理和环路滤波器的参数设计方法,然后利用ADS软件对锁相环的环路滤波器进行了设计和仿真。最后,将设计的环路滤波器应用于实际电路,并给出了测试结果。PLL is widely used in communications,navigation,telemetry and many other fields for its high integration,good phase noise and spurious characteristics. For PLL frequency synthesizer,the design of loop filter has a decisive influence on the whole performance. In this paper,we design the multiplier in accordance with the requirement to microwave signal by the Rb atomic clock through digital PLL technology. First,we discuss the basic principle of the PLL and the design method of the parameters for the loop filter. Then we designed and simulated a loop filter for PLL by ADS according to demand.Finally,we applied the design to the circuit and presented the test results.

关 键 词：倍频 锁相环 环路滤波器 仿真 相位噪声 

分 类 号：TN742[电子电信—电路与系统]