基于阵列处理器的去块滤波算法并行化设计  

A paralleling design for deblocking filtering algorithm based on array processor

作　　者：谢晓燕 石鹏飞 徐卫芳 

机构地区：[1]西安邮电大学计算机学院,陕西西安710121

出　　处：《西安邮电大学学报》2017年第5期67-72,共6页Journal of Xi’an University of Posts and Telecommunications

基　　金：国家自然科学基金资助项目(61772417;61602377;61272120);陕西省重点研发计划资助项目(2017GY-060);陕西省科技统筹创新工程资助项目(2016KTZDGY02-04-02)

摘　　要：针对多视点视频编码中去块滤波算法处理复杂、计算耗时等问题,通过分析去块滤波算法的可并行性和数据相关性,提出了一种并行化映射方案。利用面向视频编解码的动态可编程可重构阵列处理器DPR-CODEC(Dynamic Programmable Reconfigurable array processor)平台,设计并实现了基于阵列处理器的去块滤波并行算法。实验结果表明,该方法与单核处理器的串行实现方案相比数据加载时间降低了30.9倍、算法执行和总处理时间加速比分别达到12.3和28.0,有效减少了视频编解码时间,提高了去块滤波算法的运算效率。Based on analyzing the parallelism and data dependency of deblocking filtering algorithm in multi-view video coding,a feasible parallel mapping scheme is presented for enhancing the efficiency in light of the complexity and time-consuming problem.The scheme based on a DPR-CODEC platform,which is a dynamic programmable reconfigurable array processor for video codec designed by our team.Experimental results show that,compared with that serial implement on a single-processor,the proposed algorithm of deblocking filtering on the multiprocessor gains speedup ratio as high as 30.9,12.3 and 28.0 times respectively in the data loading,algorithm execution and total processing time.The method reduces the coding time effectively,and improves processing efficiency of deblocking filtering procedure.

关 键 词：视频编码 去块滤波 阵列处理器 并行化 

分 类 号：TN919.81[电子电信—通信与信息系统]