A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication  

作　　者：CAO Zhengcai HUANG Zhexiao LIU Min 

机构地区：[1]College of Information Science and Technology,Beijing University of Chemical Technology [2]Symbolic Computation and Knowledge Engineering of Ministry of Education,Jilin University [3]Department of Automation,Tsinghua University

出　　处：《Chinese Journal of Electronics》2017年第5期912-918,共7页电子学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.51375038);the Doctoral Fund of Ministry of Education of China(No.20130010110009);the Beijing Municipal Natural Science Foundation(No.4162046)

摘　　要：This paper deals with lot merging problem in semiconductor wafer fabrication system.There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same,an improved lot merging method is presented by grouping lots belonging to different orders.Based on job information extracted from the buffers,several bin packing and knapsack solving algorithms are used to determine which lots should be merged.An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots.The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress.Applied to a simulation semiconductor manufacturing fab,the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.This paper deals with lot merging problem in semiconductor wafer fabrication system.There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same,an improved lot merging method is presented by grouping lots belonging to different orders.Based on job information extracted from the buffers,several bin packing and knapsack solving algorithms are used to determine which lots should be merged.An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots.The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress.Applied to a simulation semiconductor manufacturing fab,the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.

关 键 词：Semiconductor wafer fabrication Lot merging SIMULATION Bin packing 

分 类 号：TN305[电子电信—物理电子学]