A Multi-instruction Streams Extension Mechanism for SIMD Processor  

作　　者：PENG Yuanxi ZHOU Feng HAI Yue WANG Yaohua 

机构地区：[1]National University of Defense Technology,Changsha 410000,China

出　　处：《Chinese Journal of Electronics》2017年第6期1154-1160,共7页电子学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61402493);the Research Project of National University of Defense Technology(No.GC-14-06-02)

摘　　要：Multi-media applications contain multibranches loop, it is of low efficiency to map them into traditional Single instruction multiple data(SIMD) structures. Considering the above matter, we proposed a multiinstruction streams extension method for traditional SIMD structures. The main idea is to simultaneously dispatch multiple instruction streams to multiple lanes. Compared with traditional SIMD whose lanes receive the unified single instruction stream but execute conditionally through a lane mask vector, Multi-instruction streams extension grants each of its lanes the ability to receive and execute the instructions of one particular branch path. Thus, it is of high efficiency to map multi-branches loop in applications. The design is finally implemented through Verilog language, and then integrated into the FT-Matrix vector-SIMD chip. Application profiling results shows that the proposed method consumes mere 2.61% area overhead while obtains about 1.8x to 2.4x performance gain.Multi-media applications contain multibranches loop, it is of low efficiency to map them into traditional Single instruction multiple data（SIMD） structures. Considering the above matter, we proposed a multiinstruction streams extension method for traditional SIMD structures. The main idea is to simultaneously dispatch multiple instruction streams to multiple lanes. Compared with traditional SIMD whose lanes receive the unified single instruction stream but execute conditionally through a lane mask vector, Multi-instruction streams extension grants each of its lanes the ability to receive and execute the instructions of one particular branch path. Thus, it is of high efficiency to map multi-branches loop in applications. The design is finally implemented through Verilog language, and then integrated into the FT-Matrix vector-SIMD chip. Application profiling results shows that the proposed method consumes mere 2.61% area overhead while obtains about 1.8x to 2.4x performance gain.

关 键 词：Multi-instructions extension Multibranches loop Single instruction multiple data(SIMD) structure 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]