Fully Pipelined Soft Vector Processor as a CPU Accelerator  

作　　者：PANG Yeyong WANG Shaojun PENG Yu PENG Xiyuan 

机构地区：[1]Department of Automatic Test and Control,Harbin Institute of Technology,Harbin 150080,China

出　　处：《Chinese Journal of Electronics》2017年第6期1198-1205,共8页电子学报（英文版）

基　　金：supported partly by the National Natural Science Foundation of China(No.61301205,No.61571160);the Fundamental Research Funds for the Central Universities(No.HIT.NSRIF.201615);the New Direction of Subject Development in Harbin Institute of Technology(No.01509421);the Twelfth Government Advanced Research Fund(No.9140A17050114HT01054)

摘　　要：FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations.Compared with Central processing unit(CPU), Digital signal processor(DSP), Altera C2H tool and Open CL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively.FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations.Compared with Central processing unit（CPU）, Digital signal processor（DSP）, Altera C2H tool and Open CL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively.

关 键 词：FPGA Vector processor MICROPROCESSOR ACCELERATOR 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]