基于FPGA的并串转换电路硬件实现  

Hardware implementation of parallel-to-serial circuit based on FPGA

作　　者：刘焱[1] 周圣泽 罗军[1] 王小强[1] 罗宏伟[1] 

机构地区：[1]工业和信息化部电子第五研究所,广东广州510610

出　　处：《电子技术应用》2017年第12期21-24,28,共5页Application of Electronic Technique

摘　　要：并串转换电路在通信接口中具有广泛的应用,可编程逻辑阵列由于具备灵活、可重构等特点非常适应于并串转换硬件电路的实现。为了解决硬件电路结构中资源与性能的矛盾,分析比较了移位寄存器、计数器与组合逻辑条件判定三种不同的并串转换硬件电路结构,并通过设计仿真对其进行了功能验证和性能评估。实验结果表明采用移位寄存器的实现方法具有最优的速度性能,采用计数器的实现方法具有最优的性价比,采用组合逻辑条件判定的实现方法具有最少的寄存器资源消耗,可根据实际应用需求合理选择并串转换硬件电路实现方式。Parallel-to-serial circuit has a wide application in communication interfaces. Field programmable gate array（FPGA） is very suitable for hardware implementation of parallel-to-serial circuit for its flexible and programmable. To find the best trade-off of cost and performance of hardware circuit, the methods of shift register, counter and judgment of combinational condition are imple-mented and compared. Functional verification and performance evaluation are completed based on FPGA. Experiment result has shown that the highest speed can be obtained by the method of shift register, and the best trade-off can be achieved by the method of counter. Besides, lowest registers can be consumed by using the method of combinational judgment. It relies on the ap-plication requirement to choose the best hardware architecture.

关 键 词：可编程逻辑阵列 并串转换电路 硬件实现 移位寄存器 计数器 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]