基于FPGA的可消除高频非线性的动态分频鉴相器  

Phase discriminator with dynamic frequency division for eliminating nonlinearity at high frequency based on FPGA

作　　者：杨三三 贾豫东[1] 张晓青[1] 杨博[2] 

机构地区：[1]北京信息科技大学光电测试技术北京市重点实验室,北京100192 [2]国防科学技术大学电子科学与工程学院,湖南长沙410073

出　　处：《电子技术应用》2017年第12期55-58,共4页Application of Electronic Technique

基　　金：国家级大学生创新创业训练计划支持项目(201711232011)

摘　　要：提出了一种可消除高频非线性的动态分频鉴相器的结构和实现方法,输入信号经波形变换后,利用FPGA进行分频,并通过8位拨码开关来设置1~255不同的分频系数,分频后通过数字鉴相器、低通滤波器和调理放大电路实现鉴相。这种设计不仅大大提高了鉴相范围和灵敏度,而且消除了高频非线性化现象。实验表明,该数字鉴相器输入频率范围200 kHz^100 MHz,鉴相范围-510π^+510π,线性度优于±1.5%,同时具有根据不同应用需求进行动态分频的特点。This paper presents the structure and implementation of a phase detector with dynamic frequency division for eliminating nonlinearity at high frequency. After the waveform transformation, the frequency of input signal is divided into 1 ~ 255 different parts by FPGA, and the division factor can be set by 8 bit dial switch. After frequency division, digital phase detector, low pass filter and modulation and amplifying circuit, the function of phase discrimination is realized. The discrimination range and sensitivity are improved greatly and the nonlinear phenomenon at high frequency is also eliminated. The experiment results show that the input ranges of frequency is 200 kHz ~ 100 MHz, the phase can reach -510 π ~ ＋ 510 π and linearity is better than ± 1. 5 % for the phase detector. Simultaneously, the dynamic frequency division is realized according to different application requirements.

关 键 词：高速比较器 FPGA 分频 高线性度 鉴相电路 

分 类 号：TN763.3[电子电信—电路与系统]