基于FPGA的一种μC/OS-Ⅱ硬件加速器设计  

Design of a μC/OS-Ⅱ Hardware Accelerator Based on FPGA

作　　者：徐向权 王正彦[2] 范延滨 

机构地区：[1]青岛大学计算机科学技术学院,山东青岛266071 [2]青岛大学电子信息学院,山东青岛266071

出　　处：《青岛大学学报（工程技术版）》2017年第4期90-94,共5页Journal of Qingdao University(Engineering & Technology Edition)

基　　金：青岛市建设事业科技发展专项(JK2015-25)

摘　　要：为了让实时操作系统更快更确定地处理复杂任务,本文以μC/OS-II为基础,采用软、硬件协同设计的方法,通过将内核中耗时和关键性的操作转移到硬件,提高系统确定性和速度。同时,采用现场可编程门阵列(field programmable gate array,FPGA)技术,实现硬件加速器的设计,中央处理器(central processing unit,CPU)与加速器的通信,通过DW8051的特殊功能寄存器总线(special function register,SFR)实现,并利用Altera公司的DE1-SoC开发板作为验证平台进行实验。实验结果表明,任务切换效率比原μC/OS-II系统提高了446倍,节省了时钟中断处理时间,提高了μC/OS-II系统的性能。该设计具有一定的实际应用价值。In order to al low real- t ime o p e ra t in g s y s tem s to deal wi th c om p le x ta s k s m o re q u ic k ly and m o re accu-rately , in this paper, based on yC/OS - II , th e h a rdw a re and s o f tw a re co-d es ign m e th o d is used to t ra n s fe r th e time consuming and key operat ion of th e k e rn e l to th e h a rd wa re , so as to achieve th e g o al o f im p ro v in g th e s y s-tem＇s certainty and speed. The d e velope d h a rdwa re a c ce le ra to rs ere s y n th e s iz e d on a f ie ld -p ro g ram m a b le gate Array , exploiting DWSOSl＇s spe cia l funct ion re g is te r bu s to re a l ize th e in te rc o n n e c t io n b e tw e e n and a c c e le ra to r. We use the Altera DEI - SoC dev elopment b o a rd to re a l ize th e d e v e lo pm e n t and v e r i f ic a t io n o f o u r e n t ire s y s-tem . Experimental resul ts show that th e ta s k s wi tc h in g e f f ic ie n c y is 446 t im e s h ig h e r th a n th a t o f th e o r ig in a l jLtC/OS-II system , and the c lock inter r upt p ro ce s s in g t ime is inc rea sed b y 100%. F in a l ly th e de s ig n has im -proved the performance of jLtC/OS-II s y s tem , and i t has a c e r ta in p ra c t ic a l a p p l ic a t io n v a lu e .

关 键 词：DW8051 FPGA μC/OS-Ⅱ调度器 定时器 

分 类 号：TP316.2[自动化与计算机技术—计算机软件与理论] TP332[自动化与计算机技术—计算机科学与技术]