基于SiGe BiCMOS工艺的25 Gbit/s跨阻放大器设计  

Design of 25 Gbit/s Transimpedance Amplifier Based on SiGe BiCMOS Process

作　　者：薛喆 何进[1] 陈婷[1] 王豪[1] 常胜[1] 黄启俊[1] 许仕龙[2] 

机构地区：[1]武汉大学物理科学与技术学院,武汉430072 [2]中国电子科技集团公司第五十四研究所,石家庄050051

出　　处：《半导体技术》2017年第12期892-895,917,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61774113;61574102;61404094);中央高校基本科研资助项目(2042014kf0238);中央高校基本科研业务费专项资金(重大培育项目)资助项目(2042017gf 0052);中国博士后科学基金资助项目(2012T50688)

摘　　要：采用0.25μm SiGe双极CMOS(BiCMOS)工艺设计并实现了一种传输速率为25 Gbit/s的高速跨阻前置放大器(TIA)。在寄生电容为65 fF的情况下,电路分为主放大器模块、两级差分模块和输出缓冲模块。相比传统的跨阻放大器,TIA采用Dummy形式实现了一种伪差分的输入,减小了共模噪声,提高了电路的稳定性;在差分级加入了电容简并技术,有效地提高了跨阻放大器的带宽;在各级之间引入了射极跟随器,减小了前后级之间的影响,改善了电路的频域特性。电路整体采用了差分结构,抑制了电源噪声和衬底噪声。仿真结果表明跨阻放大器的增益为63.6 dBΩ,带宽可达20.4 GHz,灵敏度为-18.2 dBm,最大输出电压为260 mV,功耗为82 mW。A high-speed transimpedance preamplifier（ TIA） with the transfer rate of 25 Gbit/s was designed and implemented using a 0.25 μm SiGe bipolar CMOS（ BiCMOS） process.With the parasitic capacitance of 65 fF,the circuit was devided into main amplifier module,two-level differential module and output buffer module.Compared with the traditional TIA,pseudo-differential which was realized by using Dummy form as the input stage to reduce the noise and improved the stability of the circuit.The capacitance degeneration technology was introduced at the differential stage,which effectively increased the bandwidth of the TIA.The emitter follower as the output circuit was used for each level of the TIA to reduce the impact between the front-and rear-stages and improve frequency domain characteristics of the TIA.The overall circuit used a differential structure that suppresses the power supply noise and substrate noise.The simulation results show that the gain of the TIA is 63.6 dBΩ,the bandwidth is up to 20.4 GHz,the sensitivity is -18.2 dBm,the maximum output voltage is 260 mV and the power consumption is 82 mW.

关 键 词：跨阻放大器 25 Gbit/s 伪差分输入 电容简并 SiGe双极CMOS(BiCMOS) 

分 类 号：TN433[电子电信—微电子学与固体电子学] TN722.71