基于74LS192的任意进制加法计数器的设计  

Design of mulitinary up-counter based on 74LS192

作　　者：穆玉珠[1] 王术群[1] 

机构地区：[1]西南民族大学电气信息工程学院,四川成都610041

出　　处：《西南民族大学学报（自然科学版）》2017年第6期599-602,共4页Journal of Southwest Minzu University(Natural Science Edition)

基　　金：西南民族大学2015年教改项目(2015QN09)

摘　　要：74LS192是一种双时钟集成十进制同步可逆计数器,是数字系统设计中常用的器件.分别用反馈归零法、反馈置数法以及进位输出端设计了基于74LS192的小容量任意进制加法计数器,并用反馈归零法设计了一种计数长度为68的大容量加法计数器.介绍的设计方法对广大电子爱好者设计相关计数器具有很好的指导意义.As a double-clock integrated decimal reversible counter,74LS192 is the common device in digital systems. Small ca- pacity mulitinary up-counters based on 74LS192 were designed by the methods of feedback-zeroing,feedback-loading and carry- out terminal, and one big capacity up-counter （68-module）was also designed by feedback-zeroing method. The design methods described above have great value of reference to electronics lovers to design related counter.

关 键 词：计数器 74LS192 数字电路 

分 类 号：TN709[电子电信—电路与系统]