基于CSMC 0.5微米CMOS工艺加固版图设计及实现  

Design and Implementation of Strengthening Layout Based on CSMC 0.5μm CMOS Process

作　　者：李湘君 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2017年第6期82-85,共4页Microprocessors

摘　　要：随着CMOS电路技术的高速发展,集成密度增大,低功耗设计以及系统芯片也已普及,导致电路更容易受到空间干扰的影响,从而使整个电子系统发生故障,因此有必要对电子元器件的抗总剂量、抗闩锁等能力进行加固设计。采用华晶上华半导体有限公司的0.5微米的CMOS工艺,设计可编程计数器加固版图时,对NMOS管采用环形栅结构,消除辐射感生边缘寄生晶体管漏电效应,降低总剂量效应的影响;采用双环保护结构,降低CMOS集成电路对单粒子闩锁效应的敏感性。对流片后的芯片进行试验,试验表明,版图加固设计的可编程计数器具有一定的抗单粒子闩锁和总剂量能力。With the high-speed development of CMOS circuits technology, integration density in- creases,and the low-power design and system chip is popularized,which causes the circuits more vulnera-ble to the affection from space interference so as to lead the whole electronic system to malfunction, thereby it is necessary to carry out the strengthening design to the capacity of resistanting total ionizing dose and latch-up.Using 0.5 滋 m CMOS process from CSMC-HJ,when designing strengthening layouts of programmable counters, gate-all-around structure is deployed to NMOS to eliminate the edge parasitic transistor leakage effect induced by radiation,and to depress the influence of total ionizing dose effect; double-ring guard structure is used to reduce the sensitivity of CMOS integrated circuit to single event latch-up effect.Experiment is applied to the chips after fabrication,and it shows that the programmable counters with layout strengthening design have certain capacity of resistanting single event latch-up and latch-uptotal ionizing dose.

关 键 词：可编程计数器 单粒子闩锁 总剂量 双环保护 加固设计 版图设计 

分 类 号：TN4[电子电信—微电子学与固体电子学]