一种电台中FPGA的可靠初始化逻辑设计  

A reliable FPGA initialization logic design for transceiver

作　　者：兰天[1] 

机构地区：[1]中国电子科技集团公司第十研究所,四川成都610036

出　　处：《现代电子技术》2018年第1期152-155,共4页Modern Electronics Technique

基　　金：装备预研基金资助项目(9140C020203)~~

摘　　要：在机载通信领域,由于飞机体积、重量及功耗等要求,往往需要在一个独立电台设备上实现多种通信模式,同时受限于电台的成本、功耗等因素,通常各种通信模式功能依靠FPGA的动态加载来实现。实际工程中发现,当FPGA动态加载时,由于各版本的加载时间、复位管理、时钟管理、接口时序等不一致,非常容易出现偶发的加载后功能异常,此类问题现象随机,极难定位,很容易耗费大量的人力、物力及时间。为解决上述矛盾,提出一种适合在电台中使用的FPGA初始化逻辑设计,保证不同版本的FPGA加载后能稳定工作,提升电台工作的可靠性与稳定性。实践表明,该方法简单、可靠,具有非常强的工程推广意义。In airborne communication field, it is necessary to realize the multiple communication modes in a single trans- ceiver according to the demands of the airplane＇s size, weight and power consumption. Normally the various communication mode functions are realized by FPGA dynamic loading because the factors of transeeiver＇s cost and power consumption. In practical engineering, it is found that the loading time, reset management, clock management and interface timing are inconsistent for FPGA dynamic loading of each version, the abiogenetic function anomaly after loading may occur easily. The above problem phenomenon is random and difficult to locate it, and consumes a large number of manpower, material resource and time. To solve this problem, a reliable FPGA initialization logic design for transceiver is proposed to guarantee the stable working of transceiver after different FPGA loadings, improve the reliability and stability of the transceiver. The practical results show this method is simple and reliable, and has strong engineering extended significance.

关 键 词：机载电台 成本 功耗 FPGA 动态加载 初始化逻辑 

分 类 号：TN791[电子电信—电路与系统] V243.1[航空宇航科学与技术—飞行器设计]