带通采样星载AIS非相干接收机的FPGA实现  

FPGA implementation of satellite based AIS non-coherent receiver with bandpass sampling

作　　者：唐然[1,2] 吴虹 程树军[3] 赵迎新 

机构地区：[1]南开大学电子信息与光学工程学院,天津300350 [2]天津市光电传感器与传感网络技术重点实验室,天津300350 [3]天津七一二通信广播股份有限公司,天津300462

出　　处：《电子技术应用》2018年第1期33-36,共4页Application of Electronic Technique

摘　　要：针对星载船舶自动识别系统(AIS)接收机接收信号带宽窄、多普勒频偏大,以及系统复杂度要求低的特点,在FPGA上设计了一种带通采样的AIS非相干接收机,采用两级数字下变频结构来降低FPGA处理压力,并减少逻辑资源消耗;采用数字鉴频和低通滤波的方法实现AIS信号的非相干解调。在AD9246+Xilinx xc4vlx80 FPGA的核心板上进行了AIS信号的解调测试,验证设计的正确性。该设计方案占用资源少,有利于AIS设备的小型化,并降低了硬件成本。The satellite based automatic identification system（AIS） receiver is known to have a narrow signal bandwidth, high Doppler frequency drift and a requirement for low complexity. This paper designs a bandpass sampling AIS noncoherent receiver on FPGA.A two-stage digital down conversion structure is adopted to reduce the FPGA processing pressure and the logic resource consump-tion. The digital frequency discriminator cascaded by a low pass filter is implemented to achieve non-coherent demodulation of AIS signal. In the AD9246 plus Xilinx xc4 vlx80 FPGA core board, the AIS signal demodulation is tested to verify our design.The proposed design consumes less resource, and is conducive to the miniaturization of AIS equipment as well as hardware costs reduction.

关 键 词：带通采样 GMSK 非相干解调 数字鉴频 FPGA 

分 类 号：TN92[电子电信—通信与信息系统]