基于4通道时间交织的FPGA高速采样系统  

FPGA high-speed sampling system based on 4 channel time-interleaved

作　　者：李宇[1,2] 刘崇庆[2,3] 吕立钧 谭洪舟[3] 

机构地区：[1]广东药科大学信息工程学院,广东广州510006 [2]华为技术有限公司,广东深圳518129 [3]广东顺德中山大学-卡内基梅隆大学国际联合研究院,广东顺德528300

出　　处：《电子技术应用》2018年第1期52-56,共5页Application of Electronic Technique

基　　金：国家自然科学基金(61473322;81570904)

摘　　要：时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。Time-interleaved sampling is an effective way to improve the sampling rate of the analog-digital converter. For evalua-tion of channel mismatch error correcting method, a high speed field-programmable gate array（ FPGA） sampling system is presented,which is based on 4 channel time-interleave. It consists of front-end analog circuit module, sampling array module, multi-phase clock circuit module and FPGA logic module for data buffering and processing. The sampling output data of system are transmitted to upper computer then the performance index is analyzed and displayed. Experiment test result shows that it can work stably on1 GS/s sampling rate after digital back-end error correction. Its significant bit and signal-to-noise ratio is 7. 03 bit and 44. 1 d B respectively. It is suitable for the verification and evaluation work of the sampling mismatch correction methods.

关 键 词：时间交织 采样系统 FPGA 多相时钟电路 失配校正 

分 类 号：TN957.5[电子电信—信号与信息处理]