用于图像压缩系统的SDRAM控制器设计  

Design of SDRAM controller for image compression system

作　　者：吴聪睿 张忠伟 张学全 

机构地区：[1]中国科学院大学,北京100190 [2]中国科学院国家空间科学中心,北京100190

出　　处：《电子设计工程》2018年第1期178-182,188,共6页Electronic Design Engineering

摘　　要：为解决基于FPGA的图像压缩系统中图像接收端速率与图像处理速率不匹配的矛盾,设计一种SDRAM控制器作为数据缓存器。作为一种大容量、高速率的存储器,SDRAM有着很广泛的应用。本文介绍了SDRAM控制器的系统结构、工作原理和工作时序。从应用需求出发,设计了SDRAM控制器的工作状态机,采用了高效的突发读操作与突发写操作,为了简化状态机工作流程,使用了自动化的初始化、自刷新、状态跳转操作。该SDRAM控制器完成了仿真验证,系统占用资源小,数据读写处理实时,综合可靠性高,通用性强,有良好的应用价值。In order to solve the contradiction between image receiving rate and image processing rate in FPGA-based image compression system, a SDRAM controller is designed as a data buffer. As a highcapacity high-speed memory, SDRAM has a very wide range of applications. This paper describes the SDRAM controller system architecture, working principle and timing analysis. In order to simplify the work flow of the state machine, the automatic initializing, self-refreshing and state jumping operations are used to simplify the work flow of the state machine. The working state machine of the SDRAM controller is designed from the application requirements, and the efficient burst read operation and burst write operation are adopted. The validity of the SDRAM controller is demonstrated by simulation example.The system takes fewer resources, perform real-time process for datum, has the very high accuracy,versatility, and has good application value.

关 键 词：SDRAM控制器 现场可编程门阵列 状态机 数据缓存 

分 类 号：TN402[电子电信—微电子学与固体电子学]