一种低相位噪声的UHF频段小数分频频率综合器  

A Low-Phase-Noise UHF-Band Fractional-N Frequency Synthesizer

作　　者：田荣倩 李浩明 刘家瑞[2] 王晓锋 王志宇[2] 虞小鹏 

机构地区：[1]浙江大学电气工程学院,杭州310027 [2]浙江大学航空航天学院,杭州310027

出　　处：《半导体技术》2018年第1期24-30,74,共8页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61574125);浙江省自然科学基金资助项目(LY16F040001);中央高校基本科研业务费专项资金资助项目(2017QN81002)

摘　　要：提出并实现了一款采用相位噪声优化技术的特高频（UHF）频段小数分频频率综合器,其工作频率为0.8-1.6 GHz。采用死区消除技术减少了鉴频鉴相器和电荷泵的噪声对系统的影响。采用分布式变容管结构和二阶谐波滤除技术设计压控振荡器,使压控振荡器获得了更低的相位噪声。采用新型的陷波滤波技术设计Δ-Σ调制器,进一步降低带内相位噪声和系统的杂散。采用TSMC 180 nm CMOS工艺进行了流片验证。测试结果表明该频率综合器在0.01,1和10 MHz频偏处的最大相位噪声分别为-95,-127和-146 dBc/Hz,杂散抑制低于-81 dBc,而频率综合器芯片的功耗仅为20 mW,芯片面积为2.5 mm×1.1 mm。An ultrahigh frequency（ UHF） band fractional-N frequency synthesizer with phase noise optimization technique was proposed and implemented,with an operating frequency of 0. 8-1. 6 GHz.The dead-zone elimination technique was adopted to reduce the noise influence induced by the phase frequency detector and charge pump on the system. The distributed varactor structure and second-order harmonic filtering technique were adopted in the voltage-controlled oscillator to achieve lower phase noise.The new type of notch filtering technique was adopted in the Δ-Σ modulator to further mitigate the inband phase noise and system spurs. The synthesizer was fabricated and verified in TSMC 180 nm CMOS process. The test results show that the proposed synthesizer achieves a maximum phase noise of -95,-127 and-146 dBc/Hz at 0. 01,1 and 10 MHz offset,with the spurious suppression less than -81 dBc and the power dissipation of only 20 mW. The chip area is 2. 5 mm×1. 1 mm.

关 键 词：频率综合器 特高频(UHF) 鉴频鉴相器(PFD) 压控振荡器(VCO) 相位噪声 Δ-Σ调制器 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN74