Area-efficient analog decoder design for low density parity check codes in deep-space applications  

作　　者：Zhao Zhe Gao Fei Zheng Hao Yin Xue 

机构地区：[1]School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2017年第4期69-75,共7页中国邮电高校学报（英文版）

摘　　要：Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.

关 键 词：low density parity check （LDPC） code analog decoding iterative message-passing algorithms hardware efficient area utilization 

分 类 号：TN911.22[电子电信—通信与信息系统]