一种应用于SOC时钟的锁相环设计  

A Design of PLL for SOC Clock Generation

作　　者：吉新村 徐严[1] 郭风岐 夏晓娟 郭宇锋 

机构地区：[1]射频集成与微组装技术国家地方联合工程实验室,南京210023 [2]南京邮电大学,南京210023

出　　处：《固体电子学研究与进展》2017年第6期406-409,437,共5页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(61704088);江苏省自然科学基金资助项目(BK20130880)

摘　　要：设计实现了一种应用于SOC的锁相环(PLL)时钟电路。提出了一种环形压控振荡器(VCO)压控增益的线性化补偿技术,通过AMOS和PMOS并联的方式构成可变电容,该锁相环采用了三级环形压控振荡器,测试结果显示VCO压控增益(KVCO)在183~284 MHz/V之间,与采用单独AMOS作为负载的环形振荡器相比,KVCO变化量下降了82%,降低了VCO的非线性。同时该锁相环通过降低鉴频鉴相器比较频率,增加环路分频比,提高振荡器的输出频率和降低电荷泵电流等方式,以降低锁相环环路滤波电容的面积。本PLL采用SMIC 55nm CMOS工艺实现,整体面积约为0.048mm^2,电源电压为1.2V,功耗1.2mW。芯片相位噪声测试结果显示,在输出100MHz时,均方根(rms)抖动为293ps(1kHz^10 MHz积分),相位噪声为-95dBc/Hz@1MHz。A Phase Locked Loop（PLL）clock generation circuit for System on Chip（SOC）was designed.A linear VCO gain（Kvco）compensation technique for the ring oscillator was proposed,the capacitance-voltage（C-V）curve of the Voltage Controlled Oscillator（VCO）was linearized by combining an accumulation MOS（AMOS）varactor and a p-channel MOS（PMOS）varactor in parallel.A three-stage ring VCO was applied for the PLL,and the measured results show that the KVCOis between 183 and 284 MHz/V,of which the variation is reduced by 82%compared to the ring oscillator with AMOS-only varactor.To reduce the capacitor area of the PLL loop filter,the comparison frequency of the phase frequency detector was reduced,as well as the charge pump current.Meanwhile,the loop division ratio and the output frequency of the oscillator were increased.This PLL was fabricated by the SMIC 55 nm CMOS process,the chip area is about 0.048 mm-2,the power consumption is 1.2 mW under a supply voltage of 1.2 V.The measured results show that at the 100 MHz output,the integrated root mean square（rms）jitter is293 ps from 1 kHz to 10 MHz,and the out-of-band phase noise are-95 dBc/Hz at 1 MHz offset.

关 键 词：锁相环 环形压控振荡器 频率调谐曲线 线性化 

分 类 号：TN432[电子电信—微电子学与固体电子学]