基于FPGA的波特率连续可调的UART接口设计  

Design of Baud Rate Configurable Uart based on FPGA

作　　者：吴志勇 郭元兴[1] 刘雨沁 WU Zhi-yong;GUO Yuan-xing;LIU Yu-qin(No.30 Institute of CETC, Chengdu Sichuan 610041, China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《通信技术》2018年第1期252-256,共5页Communications Technology

摘　　要：在FPGA上设计了一种波特率连续可调的UART接口,该接口符合RS-232C通信协议。将波特率转换为比特持续时间,在固定工作时钟频率下通过改变比特持续时间来实现波特率的连续可调,并将比特持续时间和中断时间间隔作为接口参数,用户可以灵活设置接口速率和中断CPU的频率。在接收端高速采样,采用大数判决的方式确定当前比特值,有效过滤了信号线上的毛刺,提高了UART接口的抗干扰能力。该接口已在实际项目中应用,经验证其工作稳定可靠,数据通信完全正确。A continuous and adjustable baud-rate UART interface conformable to RS-232C communication protocol is designed on FPGA. Baud rate is converted to bit duration. At constant working clock frequency, the baud rate can be continuously adjusted by changing bit duration, while the bit duration and the interruption interval are used as interface parameters. The rate of interface and the frequency of interrupting the CPU can be set flexibly by users. At the receiver, high-speed sampling is adopted, and the current bit value is determined by the way of majority decision, thus effectively filtering out the burr on the signal line and improving the anti-interference ability of UART interface. The interface is now applied to the actual project. The experiment indicates that this interface is stable and reliable in work and the data communication is completely correct.

关 键 词：通用异步收发器 FPGA 波特率可调 大数判决 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]