基于多级CIC滤波器的相控阵延时算法设计  

The time delay of ultrasonic phased array based on multistage CIC filter

作　　者：尹子骞 秦云[1] 骆英 徐桂东 

机构地区：[1]江苏大学机械工业"机械结构损伤检测评估技术"重点实验室,江苏镇江212013 [2]高端装备关键结构健康管理国际联合研究中心,江苏镇江212013

出　　处：《信息技术》2018年第1期1-4,9,共5页Information Technology

基　　金：国家自然科学重点国际合作项目(11520101001);国家自然科学青年基金(11402101)

摘　　要：为实现超声相控阵精确延时的接收技术,基于多级级联积分梳状数字滤波器(Cascade Integrator Comb,CIC)设计了延时算法。利用数字信号的内插理论,通过多级CIC数字滤波器插值处理,提高信号延时精度,同时也减少硬件资源的消耗。通过现场可编程门阵列(FPGA)的实现,验证了延时算法的可行性。实验表明此方法在采样率为50MHz的条件下可以实现1.25ns延时精度,为精度要求高的相控阵接收系统提供了技术支持。In order to achieve the ultrasonic phased array accuracy delay of receiving technology,the delay algorithm is designed based on cascade integrator comb（ CIC）. Using the digital signal interpolation theory,through the multi-level multi-level CIC digital filter interpolation processing it improved the signal delay accuracy,but also reduced the consumption of hardware resources. The feasibility of the delay algorithm is verified by the implementation of field programmable gate array（ FPGA）. The experiments show that this method can achieve 1. 25 ns delay accuracy under the condition of sampling rate of 50 MHz,and provides technical support for phased array receiving system with high precision.

关 键 词：超声相控阵 多级级联积分梳状滤波器 延时精度 现场可编程门阵列 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]